1. Field of the Invention
The present invention generally relates to packaging, carriers and circuit and module boards for electronic devices and, more particularly, to the formation of reliable and robust connections between wiring layers of laminated structures for such components.
2. Description of the Prior Art
Semiconductor devices and integrated circuits, in particular, are in widespread use in electrical and electronic devices of many types. Regardless of application, however, electrical connections must be made to other devices for semiconductor devices and integrated circuits to operate and to perform a useful function. At the same time, the mechanical environment of such electronic components is extremely important to provide mechanical protection and heat dissipation as well as supporting the integrity of electrical connections within and to the exterior of an electronic device package. Such connections have become increasingly complex and of fine connection pitch as integration density of integrated circuits has increased in response to demands for increased functionality and performance as well as potential manufacturing-economy; often requiring more connections to and between chips and forming complex networks.
Such packaging structures are known and have been developed to function at numerous levels extending from inter-chip connections (e.g. where chips are stacked or otherwise placed in close physical proximity and interconnected), to lead frames and the like for individual or multiple chip packages, to modules which can interconnect many chips with very short interconnects-and to boards which may function to carry many modules or discrete devices. Increased integration density and increased complexity of various electronic apparatus have led to extreme complexity of the connections made by the packaging structures. At the present time, a large number if not the vast majority of interconnection and packaging structures have plural layers of patterned conductors in order to provide the required interconnectivity at different levels within particular electronic apparatus.
The increasing variety of applications of electronic apparatus is accompanied by an increased range of environmental conditions of temperature, humidity, mechanical stress and the like while the increased performance of individual components generally leads to similarly wide variations in more or less localized regions within the apparatus; both of which cause increased electrical, thermal and mechanical stress at each level of interconnect and packaging structures. At the same time, the increased complexity and closeness of manufacturing tolerances of interconnect and packaging structures tends to increase susceptibility to damage or sensitivity to such stresses that may degrade performance or reliability.
Of particular concern, with the increased utilization of layered interconnect structures is vertical interconnects which extend through and between layers of insulator which carry connection patterns. These connections generally take the form of drilled and plated through holes (sometimes referred to as vias when formed by filling of a hole in a core, possibly by deposition processes other than plating) that intersect the desired layers for electrical interconnection. Substantial difficulties of fabrication are presented by increasing requirements of registration accuracy as conductors are formed at finer pitches on the surfaces of individual substrates. As a consequence, the plated through holes must become even smaller and more accurately located. Further, integrity of the mechanical joining of boards must be assured in order to avoid concentration of forces in the vertical electrical connections. Conversely, the formation of vertical connections must not compromise the mechanical joining of lamina or the dielectric properties of the lamina or insulating material interposed between them or require excessively costly processes.
For example, substantially the only practical technique for forming an integral vertical connection through a plurality of lamina is drilling through holes in an insulator, often referred to as a dielectric, with high location accuracy and plating the interiors thereof using a plurality of plating and/or filling processes to obtain adequate conductor cross-sectional area, resulting in a so-called plated through hole (PTH) structure. (The term plated through hole or the acronym PTH will be used hereinafter to collectively refer to both plated through holes and vias; to which the invention is also fully applicable.) For long vertical connections, such a process is, however, much more expensive, difficult and generally of lower yield than bonding between conductors formed on individual lamina, even though the latter type of construction does not form a similarly integral (e.g. one-piece) structure. In general, through holes having an aspect ratio of more than about 10:1 (or lower as the diameter decreases) cannot be reliably plated or filled to form a connection.
Therefore, formation with a plurality of thinner lamina having aligned plated through holes is virtually the only available technique for forming small vertical connections through a thick insulator of an interconnection structure. However, the bonding process must be accomplished within a relatively small heat budget to avoid compromise of the insulator. Thicker insulators and longer vertical connections generally require increased heat exposure of the insulator either to achieve sufficient temperatures for bonding (by solder reflow) at the interior of a thick stack of lamina or to perform bonding of thinner stacks of lamina in separate operations.
More specifically, the bonding of connections formed on individual lamina presents several problems in that the bond must be reliably formed in a near-ideal configuration to be robust, high temperature involved in the bonding process is likely to degrade or possibly even destroy dielectric properties of insulators and known bonding processes involve mechanisms that are likely to complicate or compromise accurate registration between lamina and points where vertical connections are to be formed.
For example, solder bonding between connections involves the difficulty of controlling the location of molten solder which may bond less than the intended surface area of a contact ad reducing strength and increasing electrical resistance, while solder flowing out of the intended connection may cause shorting between conductors. Temperatures at which most solder alloys (e.g. except for eutectic and near-eutectic low melting point solders) will flow or reflow are also well above the temperature at which epoxy and other board insulator materials will begin to decompose. While dielectrics can tolerate transient solder reflow temperature excursions, extended high temperature dwells are generally required for reflow to form a plurality of internal connections in a multi-layer laminate structure since the heat for melting the solder material must be supplied in addition to the heat required for the structure to reach the temperature of the melting point of the solder. Low temperature solders present additional process difficulties since they melt during any other solder bonding process and other solder processes cannot be performed selectively thereto.
Also, the more or less viscous molten solder collapses to some degree in the vertical direction and may allow lateral shifting of lamina away from a properly registered position. This latter problem is also true of conductive adhesives which may be used at lower temperatures but which do not generally develop optimal mechanical strength unless a heat treatment (e.g. curing or sintering) is also applied that poses additional problems similar to solder.
That is, some finite amount of deterioration of insulators will occur at temperatures well below the melting point of solder or the curing or drying processes required for conductive adhesives; both of which also involve properties which may compromise registration of lamina and/or movement of materials in an uncontrolled manner that can decrease manufacturing yield. In regard to insulator deterioration, short exposure to high temperature does not cause significant damage but the amount of damage caused is cumulative if additional heat exposure is required for other processes, especially field repairs where temperature cannot be well controlled.
Even more sophisticated and recently developed metallurgical techniques have not solved these problems. For example, so-called transient liquid phase (TLP) techniques use differing mutually soluble metals so that as the temperature approaches the melting point of either, alloying takes place forming a eutectic alloy of reduced melting point. As more of the lower melting point metal goes into solution, the melting point of the alloy rises and solidifies as a transiently liquid interface progresses through the bond.
The benefits of TLP processes thus derives from the fact that the temperature can be minimized and that the resulting bond will have a higher melting point than the temperature used to form the bond while some reduction in dimensional change is derived from the fact that the molten interface is limited to a relatively small thickness. This may be an important point of concern if subsequent process requires high temperature concerns for assembly or may be exploited since the bond can be returned to the bonding temperature or somewhat higher temperature without affecting the TLP bond. However, even this small thickness may be sufficient to allow compromise of registration by shifting of lamina and the temperatures required for TLP are well above temperatures that can cause damage in most dielectrics and, in any case, the material set for dielectrics and metals for TLP processes (which also require extended time for the transiently liquid interface to progress through the bond) necessarily imposes a very narrow process window as well as limiting the materials which can be employed.
It is therefore an object of the present invention to provide a technique of forming robust bonds for vertical connections between and through lamina which do not require drilling and through hole plating of lamina stacks and which can be carried out without compromise of registration of lamina or thermal damage to dielectric materials.
It is another object of the invention to provide a technique of forming a robust bonded vertical interconnection structure using a low temperature process well below the melting point of metals in the bond.
It is a further object of the invention to provide a multi-level connection structure that can be manufactured at reduced cost and increased yield and which has improved dielectric properties substantially equivalent to constituent dielectric materials and improved structural integrity and robustness
In order to accomplish these and other objects of the invention, a multi-layer connection structure having vertical connections between respective lamina is provided comprising patterned conductive features on facing surfaces of respective lamina, and a region at an interface of the patterned conductive feature in which material of the patterned conductive features and a joining material are interdiffused without solution of either in the other to form a diffusion bond.
In accordance with another aspect of the invention, a process for joining substrates is provided comprising the steps of providing a first substrate having first circuitized features of electrically conductive material on an external surface thereof; providing a second substrate of an electrically conductive material on an external surface thereof wherein at least-some areas of the conductive material are located in a mirror image pattern to the first circuitized features; depositing a joining material on at least a portion of at least one of the first and second circuitized features; thereafter positioning the second substrate adjacent the first substrate with at least some of the second circuitized features or the joining material thereon in contact with the first circuitized features or the joining material thereon; and applying pressure and heat to the first and second substrates to laminate the substrates and provide a diffusion bond between the first and second circuitized features, the heat producing a temperature below a melting point of the joining material or the circuitized features.
In accordance with a further aspect of the invention, a method of forming a multi-layer connection structure having vertical connections between conductive areas on surfaces of respective lamina is provided comprising steps of applying joining material to portions of the conductive areas of at least one lamina, positioning at least two lamina with at least some of the conductive areas in registration with some of the conductive areas on another lamina, and diffusing at least one of the joining material and material of the conductive areas into the other at a temperature below the melting point of either the joining material or the material of the patterned conductive features.